Comment by datadrivenangel
Comment by datadrivenangel 5 days ago
These chips are still sent to Taiwan for packing, so it's a good step but not a complete step.
Comment by datadrivenangel 5 days ago
These chips are still sent to Taiwan for packing, so it's a good step but not a complete step.
Given that there may be a 25% chance that China invades Taiwan by 2030, having the ability to package SOTA chips in the US by 2027 seems "soon enough".
Would be interesting if China uses drones with technology from Taiwan to invade Taiwan.
I'm not sure where GP's 25% comes from. But there have been various assessments that China intends to "reunify" with Taiwan by 2030. [1] Xi Xinping has also instructed the PLA to be prepared to invade by 2027. [2]
If you then ask yourself whether China would rather invade during the Trump administration (with its tendencies towards isolationism and "deal making") or roll the dice on a subsequent U.S. administration, you might find yourself thinking that the odds actually seem considerably higher than 25% that this could happen in the next four years.
To the extent that this narrative comes via the U.S. intelligence/defense community, one has to assume that it may biased towards exaggerating the threat. I for one hope that is the case, since I do not want to see a U.S.-China conflict any time soon. At the same time, I unfortunately don't think it's likely to be completely baseless.
[1] https://media.defense.gov/2023/Apr/24/2003205865/-1/-1/1/07-...
[2] See, e.g., https://cimsec.org/the-maritime-convoys-of-2027-supporting-t... https://thehill.com/policy/defense/4547637-china-potential-t...
what is involved in the packaging process ? I believe they don't ship fully assembled chips to Taiwan only to be put in a pretty box ?
"Packaging" in this context means taking the wafer of compute die (made in Arizona), dicing it up into individual die, mounting it onto a silicon interposer (an even bigger die, no idea where that's made, but probably taiwan) along with a bunch of HBM die, then mounting that Si interposer on a somewhat larger, very fine-pitched circuit board ('substrate') that is essentially a breakout for power and high-speed I/O from the compute die. That thing is the packaged 'CoWoS' system, where CoWoS==Chip-on-wafer-on-substrate, that eventually gets attached to a 'normal' PCB.
What I've always wondered was, how is it possible to do this process (or well, the less advanced version of it, for smaller/older chips) cheaply/at massive scale, for those ICs that cost a few cents in bulk?
Like, scaling wafer (die?) production to insanely low costs makes intuitive sense. The input is sand, the process itself is just easily-parallellizable chemistry and optics, and the output is a tiny little piece of material.
But packaging sounds as though it requires intricate mechanical work to be done to every single output chip, and I just can't wrap my head around how you scale that to the point where they cost a few cents...
I'm making an educated guess but probably the cutting of chips from the wafers, placing them into the appropriate ceramic socket types (DIP, BFGA, SMD etc), soldering the line wires from chip to pin, encasing the chip, etc.
Believe it or not, sending them overseas just to be put in a box actually can be cost-effective. Like with those pears: "grown in Argentina, packaged in Thailand, sold in UK" https://www.birminghamfoodcouncil.org/2022/01/16/part-i-pear...
I think "packaging" here refers to the process of putting the silicon die in its plastic casing and connecting the die's pad to the case's pins, see https://en.wikipedia.org/wiki/Integrated_circuit_packaging
The machines and processes needed to package the individual integrated circuits are fantastically expensive but the margins are so low in that step that it's only profitable at massive scales.
So you put the fantastically expensive machines near where most of the customers are and most of the customers are in Asia.
Works the same way with fiber optic cables. Making the long skinny bits is hard and high-margin. Actually turning them into cables is easy and low-margin.
So Corning makes huge spools of fiber optic cable in Arizona, North Carolina, and New York (I think) and ships it off to Taiwan and China where it is made into the cables that you plug into stuff.
Marine shipping is just about the most fuel efficient way of moving things between any two places, by a lot. A 100,000 dwt ship can get 1050 miles per gallon per ton of cargo. It takes about a teaspoon full of fuel to move an iPhone sized device across the pacific when I ran the numbers last.
To ship things to/from these fabs by sea you have to add the cost of shipping by truck between Phoenix and (presumably) LA. Not sure how big of a difference that makes.
Interesting. Could you give a brief description of how you got that number? Eg. what factors were considered.
Those numbers match what comes up with a quick search:
https://www.extension.iastate.edu/grain/topics/EstimatesofTo...
That study uses 1,043.4 mpg for the fuel economy of a 100,000 dwt ship.
Videos of transportation ship engines are cool. Each cylinder is wide enough for a person to lay down inside it.
This is how most modern supply chains look like.
Plus, chips are small in size and cost a lot so you can fit a lot in a container. Per unit shipping costs probably come out to be pretty low. Especially when compared to the political costs and risks associated with not onshoring.
https://www.freightwaves.com/news/dsv-unveils-details-for-ne...
^certainly there's activity in that space
Your overall point is probably right, but "tens of thousands of dollars of value in each gram" seems like an exaggeration. How much does one CPU weigh?
Depends on the chip. A typical consumer processor is 100-200 mm². Wafers are about 1mm thick (actually a bit less, but close enough) and silicon has a density of 2300kg/m³. So it's 2.3mg/mm² of wafer area. The chip is then 0.23-0.46g. if it's high end and worth $1000, then the wafers are $2-4000 per gram. Probably the low end of that since the fancier chips are usually the physically bigger ones.
However, low-end processors will be worth radically less ($100 CPUs aren't 10x smaller) and things like top-end FPGAs will be worth substantially more. An Agilex 7 can be $40,000 and if it's got less then 4 grams (around 1700mm², or 41mm*41mm), the wafer is worth over $10k/gram. The entire chip is 56x56, and from the package drawing, the die appears to be around 30x30, so it exceeds the threshold.
This is assuming all the value of the retail price is the main wafer, which is also not true.
Thousands per gram, certainly seems possible, though I doubt it's even that on average across all chips, and considering that there is non-wafer content in the price. Tens of thousands is probably pushing it. However, it's certainly likely to be rather more than gold in terms of specific value ($100/g, ish). Harder to fence, though.
I'm suprised they can't ship (flat) packaging that could be used in Arizona with a simple assembly line.
If they had that packaging design then for this to make financial sense the two way shipping (and loading, unloading, custom clearance etc) would have to be less than shipping the packaging, the setup cost per unit cost of putting the chip in a box
Wait, wait. In the context of semiconductor manufacturing packaging does not mean what you think it means. It is not putting the product in a paper box.
It is about cutting the wafer into individual chips, wire bonding the silicone to pins, and covering the whole thing with epoxy.
Here is a video which explains it better: https://www.youtube.com/watch?v=7gg2eVVayA4
It would be indeed crazy if they would ship the ready chips to Taiwan just to be put in a paper box.
basically the input of the process is a wafer which looks like this: https://waferpro.com/wp-content/uploads/2016/08/Patterned-Lo...
And the output of the process is something which looks like this: https://res.cloudinary.com/rsc/image/upload/b_rgb:FFFFFF,c_p...
You are correct. I was just illustrating what kind of processes belong to the umbrella term "packaging" in the context of semiconductor manufacturing. Was not talking about what particular process are missing from the Arizona facility.
But you are right on that it is CoWoS which is the missing ingredient.
You seem to be confusing the term packaging...it is not the box, it is how the chips are assembled together to make the final product.
Right, but he assumed he knew a technical term when he didn't, which is unwise.
What does "packaging" mean in this context? I'm a total n00b when it comes to chips.
What comes to my mind is wrapping a piece of electronics in some bubble wrap and cardboard, which doesn't sound that hard...
Until 2027, yes.
https://www.tomshardware.com/pc-components/gpus/tsmc-is-repo...
"TSMC does not have an advanced packaging facility in the U.S., and its partner Amkor will only start packaging chips in Arizona in 2027. As a result, Blackwell AI silicon produced in Arizona will need to be shipped back to Taiwan for final assembly, as all of TSMC's CoWoS packaging capacity remains in Taiwan."