Comment by hollow-moe
Comment by hollow-moe 5 days ago
what is involved in the packaging process ? I believe they don't ship fully assembled chips to Taiwan only to be put in a pretty box ?
Comment by hollow-moe 5 days ago
what is involved in the packaging process ? I believe they don't ship fully assembled chips to Taiwan only to be put in a pretty box ?
What I've always wondered was, how is it possible to do this process (or well, the less advanced version of it, for smaller/older chips) cheaply/at massive scale, for those ICs that cost a few cents in bulk?
Like, scaling wafer (die?) production to insanely low costs makes intuitive sense. The input is sand, the process itself is just easily-parallellizable chemistry and optics, and the output is a tiny little piece of material.
But packaging sounds as though it requires intricate mechanical work to be done to every single output chip, and I just can't wrap my head around how you scale that to the point where they cost a few cents...
I'm making an educated guess but probably the cutting of chips from the wafers, placing them into the appropriate ceramic socket types (DIP, BFGA, SMD etc), soldering the line wires from chip to pin, encasing the chip, etc.
Believe it or not, sending them overseas just to be put in a box actually can be cost-effective. Like with those pears: "grown in Argentina, packaged in Thailand, sold in UK" https://www.birminghamfoodcouncil.org/2022/01/16/part-i-pear...
I think "packaging" here refers to the process of putting the silicon die in its plastic casing and connecting the die's pad to the case's pins, see https://en.wikipedia.org/wiki/Integrated_circuit_packaging
"Packaging" in this context means taking the wafer of compute die (made in Arizona), dicing it up into individual die, mounting it onto a silicon interposer (an even bigger die, no idea where that's made, but probably taiwan) along with a bunch of HBM die, then mounting that Si interposer on a somewhat larger, very fine-pitched circuit board ('substrate') that is essentially a breakout for power and high-speed I/O from the compute die. That thing is the packaged 'CoWoS' system, where CoWoS==Chip-on-wafer-on-substrate, that eventually gets attached to a 'normal' PCB.