Comment by Pet_Ant 3 days ago
> some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools
Isn't translating between languages something that LLMs should excel at? I mean I'm sure it's more than just pasting it into ChatGPT but if the design has been validated and it's understood, validating the translated version should be several orders of magnitude easier than starting from scratch.
That is not enough. The generated Verilog code can be very opaque which makes it very difficult to analyze in cycle-accurate simulators. It also is (afaik) mostly impossible to automatically correlate an error in the Verilog code with a specific line in the Chisel code. Also pure Verilog is often not enough. You also need tons of vendor-specific pragmas to ensure that the design synthesizes well.
This is true, but unless great care is taken to generate nice Verilog you're going to run into issues when you try to integrate standard tools like functional coverage, formal SVA, etc.
I haven't looked at the Chisel SVA but I do recall another HDL touting readable Verilog generation as a feature in response to Chisel's being bad (can't remember which one) so I guess it can't be great.
I think Veryl stands a decent chance of success precisely because it hews so closely to SystemVerilog - you don't lose access to all the feature industry uses. It's kind of the Typescript of SystemVerilog.
> Isn't translating between languages something that LLMs should excel at?
No, not at all. Unless there is a large amount of training data relevant to the translation then LLMs are likely just to make up nonsense. Chisel is a very niche hardware description language.
Very niche? That's suprising to hear. I'm not in the space, and I know it's not in the big 2/3 (is SystemVerilog distinct from Verilog), but it's been around for 13 years and even DARPA has it on their radar:
> Chisel is mentioned by the Defense Advanced Research Projects Agency (DARPA) as a technology to improve the efficiency of electronic design, where smaller design teams do larger designs. Google has used Chisel to develop a Tensor Processing Unit for edge computing
[0] https://en.wikipedia.org/wiki/Chisel_(programming_language)#...
I think it is niche in the sense that it is almost completely unused professionally. Most usage tends to be academic or hobbyist. I don’t mean to imply that it isn’t suitable for professional work, but more that it is not very easy to make work with the industrial EDA tools necessary for fabrication.
SiFive, the leading RISC-V IP vendor, with cores available (at the moment) up to around Cortex-X2 level, has been taping out chips from Chisel since 2016.
Their first chip, a 32 bit microcontroller, ran at 320 MHz on TSC 180nm, while the comparable Arm Cortex-M4 was typically limited to 180 MHz on the same process node.
The EIC7700X, using SiFive P550 cores, given nice solid Core 2 Quad (or Raspbery Pi 4) performance.
SiFive's X280 cores are being used in rad-hard Microchip chips for NASA.
This is not exactly "academic" or "hobby".
I'm not sure this sentence [from the paper] makes a lot of sense. The only thing non-standard is the use of Chisel (and then probably CIRCT to lower it into Verilog) - if you're actually taping these out, you're still feeding that to industry-standard EDA tools.
Chisel can be compiled to Verilog out of the box, and Verilog itself should have the required support from existing EDA tools. That remark from the paper may perhaps be somewhat confused.