Comment by zozbot234
Chisel can be compiled to Verilog out of the box, and Verilog itself should have the required support from existing EDA tools. That remark from the paper may perhaps be somewhat confused.
Chisel can be compiled to Verilog out of the box, and Verilog itself should have the required support from existing EDA tools. That remark from the paper may perhaps be somewhat confused.
This is true, but unless great care is taken to generate nice Verilog you're going to run into issues when you try to integrate standard tools like functional coverage, formal SVA, etc.
I haven't looked at the Chisel SVA but I do recall another HDL touting readable Verilog generation as a feature in response to Chisel's being bad (can't remember which one) so I guess it can't be great.
I think Veryl stands a decent chance of success precisely because it hews so closely to SystemVerilog - you don't lose access to all the feature industry uses. It's kind of the Typescript of SystemVerilog.
That is not enough. The generated Verilog code can be very opaque which makes it very difficult to analyze in cycle-accurate simulators. It also is (afaik) mostly impossible to automatically correlate an error in the Verilog code with a specific line in the Chisel code. Also pure Verilog is often not enough. You also need tons of vendor-specific pragmas to ensure that the design synthesizes well.