Comment by brucehoult

Comment by brucehoult 3 days ago

SiFive, the leading RISC-V IP vendor, with cores available (at the moment) up to around Cortex-X2 level, has been taping out chips from Chisel since 2016.

Their first chip, a 32 bit microcontroller, ran at 320 MHz on TSC 180nm, while the comparable Arm Cortex-M4 was typically limited to 180 MHz on the same process node.

The EIC7700X, using SiFive P550 cores, given nice solid Core 2 Quad (or Raspbery Pi 4) performance.

SiFive's X280 cores are being used in rad-hard Microchip chips for NASA.

This is not exactly "academic" or "hobby".

adrian_b 3 days ago

SiFive has been founded by "academics", including some of those who have designed Chisel.

So it is no surprise that they have used their pet language.

Except for them, the professional use of Chisel is rare, and the future of SiFive is unclear.

Regardless how good it may be, it is difficult for any hardware-description language to replace the incumbents SystemVerilog and VHDL, because all designers are too dependent on whatever the foundries or the FPGA manufacturers support.

Choosing another language is pretty much impossible, unless you translate it to either SystemVerilog or VHDL. If you do that, then it is hard to justify using another language instead of writing directly in SystemVerilog or VHDL.

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GregarianChild 3 days ago

Chisel has a compiler to Verilog. That is not the problem. Many semi-companies use a tool-chain to generate much Verilog from higher-level sources.
The rumour I heard was this: The problem with Chisel was that (at least in the past) the Chisel compiler did not preserve port structure well. So if you had a Chisel file that translated to 80M LoCs Verilog, then verified the 80M Verilog (which is very expensive), then made a tiny change to the source Chisel, the resulting new Verilog uses different port names even for the parts that were not affected by the change. (To quip: the (old?) Chisel compiler was a bit of a hash function ...) So you have to re-verify the whole 80M of Verilog. That is prohibitively expensive, compared to only reverifying the parts that truely need to change. The high verification costs forced by this problem were rumoured to nearly have sank a company.
This is a compiler problem, not a Chisel language problem. I was told that the compiler problem has been fixed since. But I did not check this.

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brucehoult 3 days ago

SiFive was founded by academics who had successfully taped out a number of processor chips. They subsequently hired many experienced industry CPU designers from Arm, Intel, AMD and others.
> the future of SiFive is unclear
What is that supposed to mean? The future of Intel is unclear. The future of Arm is unclear. The future of Tesla is unclear. The future of Boeing is unclear. That's just life in a highly competitive industry.
> Choosing another language is pretty much impossible, unless you translate it to either SystemVerilog or VHDL.
?? Which of course is exactly what Chisel has always done. Do you even know anything about it?
> If you do that, then it is hard to justify using another language instead of writing directly in SystemVerilog or VHDL.
No it is not.
Chisel enables much more abstraction than Verilog, enabling you to design not just a single CPU core but a family with very different characteristics. Diplomacy simply has no analog in the Verilog world.
Chisel, FIRRTL, CIRCT enable the same kind of optimisations on RTL as GCC or LLVM do for C code. In fact CIRCT is built on LLVM. You can emit Verilog that is optimised for different hardware technologies, including different PDKs, or FPGA vs ASIC, in a way that is completely impossible with Verilog.

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