Comment by adrian_b
SiFive has been founded by "academics", including some of those who have designed Chisel.
So it is no surprise that they have used their pet language.
Except for them, the professional use of Chisel is rare, and the future of SiFive is unclear.
Regardless how good it may be, it is difficult for any hardware-description language to replace the incumbents SystemVerilog and VHDL, because all designers are too dependent on whatever the foundries or the FPGA manufacturers support.
Choosing another language is pretty much impossible, unless you translate it to either SystemVerilog or VHDL. If you do that, then it is hard to justify using another language instead of writing directly in SystemVerilog or VHDL.
Chisel has a compiler to Verilog. That is not the problem. Many semi-companies use a tool-chain to generate much Verilog from higher-level sources.
The rumour I heard was this: The problem with Chisel was that (at least in the past) the Chisel compiler did not preserve port structure well. So if you had a Chisel file that translated to 80M LoCs Verilog, then verified the 80M Verilog (which is very expensive), then made a tiny change to the source Chisel, the resulting new Verilog uses different port names even for the parts that were not affected by the change. (To quip: the (old?) Chisel compiler was a bit of a hash function ...) So you have to re-verify the whole 80M of Verilog. That is prohibitively expensive, compared to only reverifying the parts that truely need to change. The high verification costs forced by this problem were rumoured to nearly have sank a company.
This is a compiler problem, not a Chisel language problem. I was told that the compiler problem has been fixed since. But I did not check this.