Comment by colanderman

Comment by colanderman 5 days ago

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Nice, these ideas have been around for a long time but never commercialized to my knowledge. I've done some experiments in this area with simulations and am currently designing some test circuitry to be fabbed via Tiny Tapeout.

Reversibility isn't actually necessary for most of the energy savings. It saves you an extra maybe 20% beyond what adiabatic techniques can do on their own. Reason being, the energy of the information itself pales in comparison to the resistive losses which dominate the losses in adiabatic circuits, and it's actually a (device-dependent) portion of these resistive losses which the reversible aspect helps to recover, not the energy of information itself.

I'm curious why Frank chose to go with a resonance-based power-clock, instead of a switched-capacitor design. In my experience the latter are nearly as efficient (losses are still dominated by resistive losses in the powered circuit itself), and are more flexible as they don't need to be tuned to the resonance of the device. (Not to mention they don't need an inductor.) My guess would be that, despite requiring an on-die inductor, the overall chip area required is much less than that of a switched-capacitor design. (You only need one circuit's worth of capacitance, vs. 3 or more for a switched design, which quadruples your die size....)

I'm actually somewhat skeptical of the 4000x claim though. Adiabatic circuits can typically only provide about a single order of magnitude power savings over traditional CMOS -- they still have resistive losses, they just follow a slightly different equation (f²RC²V², vs. fCV²). But RC and C are figures of merit for a given silicon process, and fRC (a dimensionless figure) is constrained by the operational principles of digital logic to the order of 0.1, which in turn constrains the power savings to that order of magnitude regardless of process. Where you can find excess savings though is simply by reducing operating frequency. Adiabatic circuits benefit more from this than traditional CMOS. Which is great if you're building something like a GPU which can trade clock frequency for core count.

mikepfrank 5 days ago

Hi, someone pointed me at your comment, so I thought I'd reply.

First, the circuit techniques that aren't reversible aren't truly, fully adiabatic either -- they're only quasi-adiabatic. In fact, if you strictly follow the switching rules required for fully adiabatic operation, then (ignoring leakage) you cannot erase information -- none of the allowed operations achieve that.

Second, to say reversible operation "only saves an extra 20%" over quasi-adiabatic techniques is misleading. Suppose a given quasi-adiabatic technique saves 79% of the energy, and a fully adiabatic, reversible version saves you "an extra 20%" -- well, then now that's 99%. But, if you're dissipating 1% of the energy of a conventional circuit, and the quasi-adiabatic technique is dissipating 21%, that's 21x more energy efficient! And so you can achieve 21x greater performance within a given power budget.

Next, to say "resistive losses dominate the losses" is also misleading. The resistive losses scale down arbitrarily as the transition time is increased. We can actually operate adiabatic circuits all the way down to the regime where resistive losses are about as low as the losses due to leakage. The max energy savings factor is on the order of the square root of the on/off ratio of the devices.

Regarding "adiabatic circuits can typically only provide an order of magnitude power savings" -- this isn't true for reversible CMOS! Also, "power" is not even the right number to look at -- you want to look at power per unit performance, or in other words energy per operation. Reducing operating frequency reduces the power of conventional CMOS, but does not directly reduce energy per operation or improve energy efficiency. (It can allow you to indirectly reduce it though, by using a lower switching voltage.)

You are correct that adiabatic circuits can benefit from frequency scaling more than traditional CMOS -- since lowering the frequency actually directly lowers energy dissipation per operation in adiabatic circuits. The specific 4000x number (which includes some benefits from scaling) comes from the analysis outlined in this talk -- see links below - but we have also confirmed energy savings of about this magnitude in detailed (Cadence/Spectre) simulations of test circuits in various processes. Of course, in practice the energy savings is limited by the resonator Q value. And a switched-capacitor design (like a stepped voltage supply) would do much worse, due to the energy required to control the switches.

https://www.sandia.gov/app/uploads/sites/210/2023/11/Comet23... https://www.youtube.com/watch?v=vALCJJs9Dtw

Happy to answer any questions.

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  • colanderman 5 days ago

    Thanks for the reply, was actually hoping you'd pop over here.

    I don't think we actually disagree on anything. Yes, without reverse circuits you are limited to quasi-adiabatic operaton. But, at least in the architectures I'm familiar with (mainly PFAL), most of the losses are unarguably resistive. As I understand PFAL, it's only when the operating voltage of a given gate drops below Vth that the (macro) information gets lost and reversibility provides benefit, which is only a fraction of the switching cycle. At least for PFAL the figure is somewhere in the 20% range IIRC. (I say "macro" because of course the true energy of information is much smaller than the amounts we're talking about.)

    The "20%" in my comment I meant in the multiplicative sense, not additive. I.e. going from 79% savings to 83.2%, not 99%. (I realize that wasn't clear.)

    What I find interesting is reversibility isn't actually necessary for true adiabatic operation. All that matters is the information of where charge needs to be recovered from can be derived somehow. This could come from information available elsewhere in the circuit, not necessarily the subsequent computations reversed. (Thankfully, quantum non-duplication does not apply here!)

    I agree that energy per operation is often more meaningful, BUT one must not lose sight of the lower bounds on clock speed imposed by a particular workload.

    Ah thanks for the insight into the resonator/switched-cap tradeoff. Yes, capacitative switching designs which are themselves adiabatic I know is a bit of a research topic. In my experience the losses aren't comparable to the resistive losses of the adiabatic circuitry itself though. (I've done SPICE simulations using the sky130 process.)

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    • mikepfrank 5 days ago

      It's been a while since I looked at it, but I believe PFAL is one of the not-fully-adiabatic techniques that I have a lot of critiques of.

      There have been studies showing that a truly, fully adiabatic technique in the sense I'm talking about (2LAL was the one they checked) does about 10x better than any of the other "adiabatic" techniques. In particular, 2LAL does a lot better than PFAL.

      > reversibility isn't actually necessary

      That isn't true in the sense of "reversible" that I use. Look at the structure of the word -- reverse-able. Able to be reversed. It isn't essential that the very same computation that computed some given data is actually applied in reverse, only that no information is obliviously discarded, implying that the computation always could be reversed. Unwanted information still needs to be decomputed, but in general, it's quite possible to de-compute garbage data using a different process than the reverse of the process that computed it. In fact, this is frequently done in practice in typical pipelined reversible logic styles. But they still count as reversible even though the forwards and reverse computations aren't identical. So, I think we agree here and it's just a question of terminology.

      Lower bounds on clock speed are indeed important; generally this arises in the form of maximum latency constraints. Fortunately, many workloads today (such as AI) are limited more by bandwidth/throughput than by latency.

      I'd be interested to know if you can get energy savings factors on the order of 100x or 1000x with the capacitive switching techniques you're looking at. So far, I haven't seen that that's possible. Of course, we have a long way to go to prove out those kinds of numbers in practice using resonant charge transfer as well. Cheers...

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      • colanderman 5 days ago

        PFAL has both a fully adiabatic and quasi-adiabatic configuration. (Essentially, the "reverse" half of a PFAL gate can just be tied to the outputs for quasi-adiabatic mode.) I've focused my own research on PFAL because it is (to my knowledge) one of the few fully adiabatic families, and of those, I found it easy to understand.

        I'll have to check out 2LAL. I haven't heard of it before.

        No, even with a fully adiabatic switched-capacitance driver I don't think those figures are possible. The maximum efficiency I believe is 1-1/n, n being the number of steps (and requiring n-1 capacitors). But the capacitors themselves must each be an order of magnitude larger than the adiabatic circuit itself. So it's a reasonable performance match for an adiabatic circuit running at "max" frequency, with e.g. 8 steps/7 capacitors, but 100x power reduction necessary to match a "slowed" adiabatic circuit would require 99 capacitors... which quickly becomes infeasible!

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  • naasking 4 days ago

    Do these reversible techniques help or hinder in applications where hardened electronics are required, like satellites or space probes? I can see a case for both.

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    • mikepfrank 4 days ago

      I believe it helps, because we don't have to reduce the bit energy as much to operate efficiently. But this would need to be studied in more detail.

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itissid 5 days ago

Can one define the process of an adiabetic circuit goes through like one would do analogusly for the carnot engine? The idea being coming up with a theoretical cieling for the efficiency of such a circuit in terms of circuit parameters?

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  • colanderman 5 days ago

    Yes a similar analysis is where the above expression f²RC²V² comes from.

    Essentially -- (and I'm probably missing a factor of 2 or 3 somewhere as I'm on my phone and don't have reference materials) -- in an adiabatic circuit the unavoidable power loss for any individual transistor stems from current (I) flowing through that transistor's channel (a resistor R) on its way to and from another transistor's gate (a capacitor C). So that's I²R unavoidable power dissipation.

    I must be sufficient to fill and then discharge the capacitor to/from operating voltage (V) in the time of one cycle (1/f). So I=2fCV. Substituting this gives 4f²RC²V².

    Compare to traditional CMOS, wherein the gate capacitance C is charged through R from a voltage source V. It can be shown that this dissipates ½CV² of energy though the resistor in the process, and the capacitor is filled with an equal amount of energy. Discharging then dissipates this energy through the same resistor. Repeat this every cycle for a total power usage of fCV².

    Divide these two figures and we find that adiabatic circuits use 4fRC times as much energy as traditional CMOS. However, f must be less than about 1/(5RC) for a CMOS circuit to function at all (else the capacitors don't charge sufficiently during a cycle) so this is always power savings in favor of adiabatics. And notably, decreasing f of an adiabatic circuit from the maximum permissible for CMOS on the same process increases the efficiency gain proportionally.

    (N.B., I feel like I missed a factor of 2 somewhere as this analysis differs slightly from my memory. I'll return with corrections if I find an error.)

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pfdietz 5 days ago

Maybe this would work better with superconducting electronics?

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  • mikepfrank 5 days ago

    There indeed has been research on reversible adiabatic logic in superconducting electronics. But superconducting electronics has a whole host of issues of its own, such as low density and a requirement for ultra-low temperatures.

    When I was at Sandia we also had a project exploring ballistic reversible computation (as opposed to adiabatic) in superconducting electronics. We got as far as confirming to our satisfaction that it is possible, but this line of work is a lot farther from major commercial applications than the adiabatic CMOS work.

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  • colanderman 5 days ago

    Possibly, that's an interesting thought. The main benefit of adiabatics as I see them is that, all else being equal, a process improvement of the RC figure can be used to enable either an increase in operating frequency or a decrease in power usage (this is reflected as the additional factor of fRC in the power equation). With traditional CMOS, this only can benefit operating frequency -- power usage is independent of the RC product per se. Supercondition (or near-superconduction) is essentially a huge improvement in RC which wouldn't be able to be realized as an increase in operating frequency due to speed of light limitations, so adiabatics would see an outsize benefit in that case.

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