Comment by dmitrygr
Comment by dmitrygr 10 months ago
Well, lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly. And no, it will not get magically fused by magic fusing fairies in your cpu
Comment by dmitrygr 10 months ago
Well, lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly. And no, it will not get magically fused by magic fusing fairies in your cpu
You’re replying to the author of the post explaining why he would have to do more in software to emulate RISC-V than MIPS and that would be more effort and run slower, and you’re telling him “that’s extremely subjective”?
How is that subjective?
"well known design deficiency" is the subjective part.
> Well, lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly.
Does it? Well, there's a vendor specific extension for that (XTheadMemIdx):
https://github.com/XUANTIE-RV/thead-extension-spec/releases/...
Not sure about GCC, but on clang it is trivial to enable it. And if you really want to (assuming you have the hardware) you could compile exactly the same code with and without it and compare how much exactly it is handicapped if those instructions are not there.
Plus, on RISC-V multiplication/division (about which you've complained) is optional, and there is also a variant of RISC-V with only 16 registers instead of 32 (also very simple to enable on recent versions of clang, although Linux would probably need some modifications to be able to run on that).
So I'm not entirely convinced that RISC-V would be worse here.