Comment by dmitrygr

Comment by dmitrygr a year ago

Well, lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly. And no, it will not get magically fused by magic fusing fairies in your cpu

kouteiheika a year ago

> Well, lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly.

Does it? Well, there's a vendor specific extension for that (XTheadMemIdx):

https://github.com/XUANTIE-RV/thead-extension-spec/releases/...

Not sure about GCC, but on clang it is trivial to enable it. And if you really want to (assuming you have the hardware) you could compile exactly the same code with and without it and compare how much exactly it is handicapped if those instructions are not there.

Plus, on RISC-V multiplication/division (about which you've complained) is optional, and there is also a variant of RISC-V with only 16 registers instead of 32 (also very simple to enable on recent versions of clang, although Linux would probably need some modifications to be able to run on that).

So I'm not entirely convinced that RISC-V would be worse here.

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dmitrygr a year ago

Lack of mul/div isn’t actually good. Having it be done ins guest code is a magnitude slower than is host code.
My other issue was that there is NO working Linux user space for rv32. There is for rv64. No Debian. No Ubuntu. No anything for rv32

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snvzz a year ago

>lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly

Is this a guess, or statistically supported on a body of empirical evidence like the RISC-V spec is?

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dmitrygr a year ago

Compile same code for aarch64 and riscv64. Compare.
It is well known design deficiency. Much like lack of bit field ops.

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- camel-cdr a year ago
  
  Do you have code examples for this? I'm looking for cases where RISC-V is lacking compared to arm.
  
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- snvzz a year ago
  
  Sounds extremely subjective.
  i.e. it does not have my favored instructions or addressing modes, so it must be worse.
  
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  jodrellblank a year ago
  
  You’re replying to the author of the post explaining why he would have to do more in software to emulate RISC-V than MIPS and that would be more effort and run slower, and you’re telling him “that’s extremely subjective”?
  How is that subjective?
  
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  Dylan16807 a year ago
  
  "well known design deficiency" is the subjective part.
  
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  smolder a year ago
  
  Much like juggling with your feet instead of hands is subjectively worse.
  
  Reply View | 2 replies