Comment by snvzz
>lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly
Is this a guess, or statistically supported on a body of empirical evidence like the RISC-V spec is?
>lack of REG+REG and REG+SHIFTED_REG addressing modes handicaps it significantly
Is this a guess, or statistically supported on a body of empirical evidence like the RISC-V spec is?
You’re replying to the author of the post explaining why he would have to do more in software to emulate RISC-V than MIPS and that would be more effort and run slower, and you’re telling him “that’s extremely subjective”?
How is that subjective?
From a hardware perspective, juggling is better without flags and without unnecessary addressing modes.
Neither are concepts RISC-V invented, but rather, adopted. Ideas that have been plenty tested out there, and proven beneficial.
Large body of evidence trumps intuition and guesswork. Most of this is documented in the spec itself and/or in:
Computer Architecture: A Quantitative Approach (John L. Hennessy, David A. Patterson)
Compile same code for aarch64 and riscv64. Compare.
It is well known design deficiency. Much like lack of bit field ops.