Comment by 201984
AArch64 also zeroes the upper 32 bits of the destination register when you use a 32 bit instruction.
AArch64 also zeroes the upper 32 bits of the destination register when you use a 32 bit instruction.
It's to break dependencies for register renaming. If you have an instruction like
mov w5, w6 // move low 32 bits of register 6 into low 32 bits of register 5
I don't know either, but why wouldn't backwards compatibility apply to aarch64? It too is based on a pre-existing 32-bit architecture.
I'm curious, why is that?
I know x86-64 zeroes the upper part of the register for backwards compability and improve instruction cache (no need for REX prefix), but AArch64 is unclear for me.