Comment by mycall

> Consumer DDR5 motherboards normally take UDIMMs. Server DDR5 motherboards normally take RDIMMs. They're mechanically incompatible, and the voltages are different.

All you need is a fixed-latency, dumb translator bridge where the adapter forces everything into a simplified JEDEC-compliant mode.

CA/CK Line Translator with a Fixed Retimer as the biggest mismatch between RDIMM/UDIMM is the command/address path.

RDIMMs route CA/CK to RCD to DRAM, and the UDIMMs route CA/CK to DRAM directly, take the UDIMM CA/CK, delay + buffer + level shift it, feed it into a "RCD" like input using a delay locked loops (DLL).

Throw in a SPD translator, PMIC and voltage correction, DQ line conditioning and some other stuff into a 10–12-layer PCB, retimer chips, vrm, and level shifters.

It would cost about $40 million to fab and about $100 per adapter but would make bank with all the spare UDIMMs when the bubble bursts.