Comment by sliken
I've been paying close attention, found various hints at anandtech (RIP), chips and cheese, and STH.
It doesn't make much difference to most apps, but I believe the single CCD (like the 9700x) has better bandwidth to IOD then their dual CCD chips, like the 9900x and 9950x
Similarly on the server chips you can get 2,4,8, or 16 CCDs. To get 16 cores you can use 2 CCDs or 16 CCDs! But the sweet spot (max bandwidth per CCD) is at 8 CCDs where you get a decent number of cores and twice the bandwidth per CCD. Keep in mind the genoa/turin EPYC chips have 24 channels (32 bit x 24) for a 768 bit wide memory interface. Not nearly as constrained as their desktops.
Wish I could paste in a diagram, but check out:
https://www.amd.com/content/dam/amd/en/documents/epyc-techni...
Page 7 has a diagram of 96 core with one GMI (IF) port per CCD and a 32 core chip two GMI ports per CCD.
That's a gen old I believe, the max CCDs is now 16, not 12 with turin.
So "GMI3-wide" and similar terms are the important things to search for.
some diagrams: https://www.servethehome.com/amd-epyc-genoa-gaps-intel-xeon-...
From another page: "The most noteworthy aspect is that there is a new GMI3-Wide format. With Client Zen 4 and previous generations of Zen chiplets, there was 1 GMI link between the IOD and CCD. With Genoa, in the lower core count, lower CCD SKUs, multiple GMI links can be connected to the CCD."
And it seems like all the chiplets have two links, but everything I can find says they just don't hook up both on consumer parts.