Comment by rightbyte
> If you have more than one core, can they introduce jitter or slowdown to each other accessing memory?
DMA and fancy peripherals like UART, SPI etc, could be namedropped in this regard, too.
> If you have more than one core, can they introduce jitter or slowdown to each other accessing memory?
DMA and fancy peripherals like UART, SPI etc, could be namedropped in this regard, too.
Plot twist: the very memory may be connected via SPI.